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Nonetheless, we test to see if it is actually fused off. Intel shot down that concept almost immediately, saying very succinctly that no Alder Lake CPU would support AVX-512. There was a thought that if Intel were to release a version of Alder Lake with P-cores only, or if a system had all the E-cores disabled, there might be an option to have AVX-512.

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By disabling AVX-512 in Alder Lake, it means that both the P-cores and the E-cores have a unified common instruction set, and they can both run all software supported on either. Experts in the area have pointed out that technically the chip could be designed to catch the error and hand off the thread to the right core, but Intel hasnвЂ™t done this here as it adds complexity. So if, naively, AVX-512 code was run on a processor that did not understand it, like an E-core, it would cause a critical error, which could cause the system to crash. One of the downsides of most operating system design is that when a new program starts, thereвЂ™s no way to accurately determine which core it will be placed on, or if the code will take a path that includes AVX-512.

Part of the issue of AVX-512 support on Alder Lake was that only the P-cores have the feature in the design, and the E-cores do not. We were told as part of the extra Architecture Day Q&A that it would be fused off, and the plan was for all Alder Lake CPUs to have it fused off. One of the issues was that the processor, inside the silicon, actually did have the AVX-512 unit there.

One of the more interesting disclosures about Alder Lake earlier this year is that the processor would not have IntelвЂ™s latest 512-bit vector extensions, AVX-512, despite the company making a big song and dance about how it was working with software developers to optimize for it, why it was in their laptop chips, and how no transistor should be left behind.

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